CMP1 – Components for 5G and beyond
Friday, 6 June 2025, 9:00-10:30, room 1.D
Session Chair: Izzat Darwazeh (Univ. College London, UK)
Indoor ISAC Demonstrator with Aperture Coupled Antennas (ACA) at Wi-Fi Band for 6G Applications
Mehrab Ramzan, Jan Adler and Shahanawaz Kamal (Barkhausen Institut, Germany); Maximilian Matthe (Barkhausen Institute, Germany); Padmanava Sen (Research Group Leader, Barkhausen Institut gGmbH, Germany)
In this paper, co-located single-element aperture coupled antennas (ACA) working at the Wi-Fi frequency band are presented. The antenna shows an operating bandwidth of 320 MHz at 6.11 GHz center frequency and exhibits an isolation of 38 dB over the desired frequency band. The mutual coupling reduction is achieved by utilizing complementary split ring resonators (CSRR) in the ground plane and the integrated antennas show a smooth measured gain of 8 dBi in the entire working frequency band. Moreover, the co-located antennas are further integrated with the software-defined radio (SDR) to demonstrate its indoor sensing capabilities up to a distance of two meters. Simultaneously, the communication performance is shown and evaluated by employing a separated horn antenna receiver in a demonstrator designed for integrated sensing and communication (ISAC) applications.
A Compact D-Band 360° Active Differential Phase Shifter for Sub-Terahertz Phased-Array Antennas in 40nm CMOS
Zhen Yan, Satoshi Tanaka, Takeshi Yoshida and Minoru Fujishima (Hiroshima University, Japan)
This study presents the design of a D-band 156-GHz phase shifter intended for transceiver circuits in phased array antennas to receive terahertz signals. The proposed phase shifter utilizes a tunable active circuit composed of series-connected NMOS transistors, where the bias voltage is controlled to adjust the drain-source resistance. This configuration enables both continuous and fixed phase shifts. The phase shift range is extended to cover the full 360° by connecting multiple adjustable phase shifter units in series, employing a 0°/60° phase shift switch, and incorporating a Gilbert cell as a 0°/180° phase switch. The circuit is fabricated using TSMC’s 40nm CMOS process, ensuring a compact layout and facilitating miniaturization. Measurement results confirmed the circuit operates effectively, demonstrating its potential for further research and practical applications.
Novel on-Wafer mmWave MIMO Antenna for JCAS of CT Scanners and Ring Resonator for Assessing Polyimide Properties at 60 GHz
Shahanawaz Kamal (Barkhausen Institut, Germany); Muhammad Umar (Barkhausen Institute, Germany); Padmanava Sen (Research Group Leader, Barkhausen Institut gGmbH, Germany); Adil Shehzad and Juliana Panchenko (Fraunhofer Institute for Reliability and Microintegration, Germany); Michael Hosemann (Siemens Healthineers, Germany)
This paper presents an on-wafer dual-port multiple-input−multiple-output (MIMO) antenna for joint communications and sensing (JCAS) of new computed tomography (CT) scanner-based medical applications in the 60 gigahertz (GHz) millimeter wave (mmW) spectrum. The proposed antenna yields a wide -10 decibel (dB) impedance bandwidth (I-BW) of 8.4 GHz from 55.8-64.2 GHz by combining radiating elements with low and high impedance. A partial ground plane was deployed to produce a noteworthy quasi-omnidirectional realized gain (𝘎ᵣ) of 6.11 dB isotropic (dBi) and a fairly elevated total efficiency (ηₜ) of 79.6%. Furthermore, reasonable antenna isolation (|S₂₁|) of >12 dB was ascertained while engaging a compact area of 5.79×8λ₀² and a low-profile of 0.1526λ₀, where λ₀ indicates free-space wavelength at 60 GHz. This paper also introduces a millimeter wave ring resonator (mmW-RR) design that is capable of determining the relative permittivity (ϵᵣ) of polyimide (𝘗𝘐) wafer at 60 GHz.
De-Embedding Method for Accurate Electromagnetic Analysis of Differential Circuits with Discontinuities
Koki Mochida, Satoshi Tanaka, Takeshi Yoshida, Shuhei Amakawa and Minoru Fujishima (Hiroshima University, Japan)
Phased array transceivers at 300 GHz enable high directivity and compact system designs for 6G communication. To meet miniaturization requirements, power matching circuits, such as transformer and transmission-line matching circuits, must be carefully designed. However, discontinuities in cross-sectional structures between components, such as MOSFETs with ground planes and transformer matching circuits without ground planes, cause boundary mismatches that degrade electromagnetic (EM) analysis accuracy. This paper proposes a four-port de-embedding method that considers discontinuities in both odd mode and even mode to improve divided EM analysis in differential circuits. The method is validated through the design of a two-stage differential amplifier, where it reduces the odd mode gain Soo21 error at 125 GHz from 0.72 dB to 0.24 dB. This method enables efficient EM analysis for large-scale layouts, such as 300 GHz phased array transceivers, without full EM analysis. It provides an accurate and computationally efficient solution for high-frequency circuit design.
Development of a Universal FPGA-Based Coprocessor for 5G NR and WLAN LDPC Coding
Lukasz Lopacinski (IHP Leibniz Institute for High Performance Microelectronics, Germany); Yiyun Jian (IHP – Leibniz Institute for High Performance Microelectronics, Germany); Muhammad Nauman (IHP Leibniz-Institut Für Innovative Mikroelektronik, Germany); Pukar Shakya (Innovations for High Performance Microelectronics, Germany); Milos Krstic (IHP, Germany); Eckhard Grass (IHP & Humboldt-University Berlin, Germany)
Low-density parity-check (LDPC) codes are widely used in modern communication systems due to their near-capacity error correction performance. This paper presents a practical FPGA implementation of a universal hardware coprocessor for LDPC encoding and decoding, focusing on a system-level architecture, achievable data rate, latency measurements, and hardware resource utilization. The LDPC coding is realized by the Xilinx hardware macros available in the Xilinx RF-SoC FPGAs. We explore various design simplifications, including core combining, memory management, and data scheduling, to achieve high throughput while maintaining the lowest implementation complexity. The proposed architecture is implemented on an FPGA platform and is equipped with 10 Gb/s Ethernet interfaces, demonstrating real-time decoding capabilities and improved performance compared to software-based approaches. Experimental results validate the design, showcasing its applicability in high-speed communication systems. This work serves as a valuable reference for engineers and researchers aiming to deploy LDPC decoding in FPGA-based environments by reusing the existing Intellectual Property (IP), which is available in Xilinx SoC without additional charges.
