CME1: Components and Microelectronics
Friday, 11 June 2021, 09:30-11:00, Zoom Room
Session Chair: Vitor Tavares (Univ. Porto, Portugal)
Design and Fabrication of Sub-THz Steerable Photonic Transmitter 1×4 Array for Short-Distance Wireless Links
Luis M. Pessoa (INESC TEC & Faculty of Engineering, University of Porto, Portugal); Luis Gonzalez Guerrero and Cyril Renaud (University College London, United Kingdom (Great Britain)); Glenn George (Bay Photonics, United Kingdom (Great Britain)); Marco A. Porcel (VLC Photonics, Spain); Henrique M Salgado (University of Porto & INESC Porto, Portugal); Bilal Hussain (Faculty of Engineering of the University of Porto, Portugal); Alberto Hinojosa (VLC Photonics SL, Portugal); Chris Graham (University College London, United Kingdom (Great Britain)); James Seddon (UCL, United Kingdom (Great Britain)); Juan Fernández (VLC Photonics, Spain)
In this paper we present the latest results on the design, fabrication and test of stand-alone photonic devices devoted to ultra-high bandwidth wireless access networks operating near the Terahertz (THz) band. We review the sub-THz photonics-based technology devices developed as part of the TERAPOD project, comprising the monolithically integrated Silicon Nitride photonic integrated circuit for phase distribution, the 1×4 array of integrated Uni-Travelling Carrier Photo-Diodes (UTC-PDs) and the radiative design of the high-frequency four element linear patch antenna array based on Benzcyclobutene (BCB) layers. We also report the suitability to assemble all those components in a robust small-form factor hybrid package.
SiGe: BiCMOS Technology is Enabling D-Band Link with Active Phased Antenna Array
Andrea Pallotta (STMicroelectronics, Italy); Pascal Roux (Nokia-Bell-Labs/III-V Lab, France); David del Río and Juan F Sevillano (CEIT and TECNUN, Spain); Mahmoud Pirbazari and Andrea Mazzanti (University of Pavia, Italy); Vladimir Ermolov, Antti E. I. Lamminen and Jussi Säily (VTT Technical Research Centre of Finland, Finland); Mario Giovanni Luigi Frecassetti (NOKIA, Italy); Maurizio Moretto (Nokia, Italy); Jesus de Cos (ERZIA, Spain)
While 5G wireless network is being currently deployed around the world, preliminary research activity has begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedented transformation of the wireless network, in comparison with previous generations, from analog and RF point of view the need to address new frequency spectrum to increase achievable data rate and its implication on the development of differentiated More-than-Moore silicon technologies will remain. This paper reviews the exploitation, in the framework of the Horizon 2020 DREAM project, of the radio spectrum in D-band (130-174.4GHz), relying on power efficient silicon-based BiCMOS FEM transceiver and active phased antenna array with beam steering functionality, demonstrating wireless links with data rate exceeding current V-band and E-band wireless backhaul solutions.
FPGA Implementation of a Wideband Multi-Gb/s 5G BF-OFDM Transceiver
Jean-Baptiste Doré (CEA, France); Marc Laugeois (CEA-LETI, France); Nicolas Cassiau (CEA-Leti Minatec Campus, France); Xavier Popon (CEA-LETI, France)
This paper describes a Field Programmable Gate Array (FPGA) implementation of a multi-Gb/s Block Filtered OFDM transceiver, fully 5G NR compatible. The main obstacles for such a work are (i) the support of multiple configurations and parameters, (ii) the high bandwidth w.r.t the board clock frequency and (iii) the intrinsic complexity of BF-OFDM. We prove that despite these barriers an hardware implementation of this waveform is possible, even with a bandwidth up to 400 MHz. We based our developments on the following pillars: smart layout of the basic modules, parallelization of dedicated functions design and ad hoc architecture. Measurements and complexity analysis demonstrate the high flexibility of BF-OFDM.
A 336 Gbit/s Full-Parallel Window Decoder for Spatially Coupled LDPC Codes
Matthias Herrmann (TU Kaiserslautern, Germany); Norbert Wehn (University of Kaiserslautern, Germany); Max Thalmaier, Markus Fehrenz, Timo Lehnigk-Emden and Matthias Alles (Creonic GmbH, Germany)
Low-Density Parity-Check (LDPC) codes are among the most powerful Forward Error Correction (FEC) schemes and part of many communication standards. Emerging use cases are expected to require data rates towards Tbit/s, which is one to two orders of magnitude higher than the throughput specified in 5G-NR. For throughputs towards Tbit/s, state-of-the-art LDPC soft decoders are restricted to short code block sizes of several hundreds to thousands of bits due to routing congestion challenges, forcing a firm limit to the overall communications performance of the transmission system. In this paper, we focus on a relatively new class of LDPC codes, denoted as Spatially Coupled LDPC (SC-LDPC) codes. For the first time, we show that these codes enable efficient, very high throughput (>> 100 Gbit/s) decoding of large code block sizes. To this end, we present an SC-LDPC decoder for a length N=51328 terminated SC-LDPC code with sub-block size c=640 and coupling width ms=1, that achieves a throughput of 336 Gbit/s in a 22nm FD-SOI technology, which is about 50 times higher than the fastest SC-LDPC decoder in literature. In contrast to existing work, the presented decoder is based on the Full-Parallel Window Decoder (FPWD) architecture. We propose algorithmic and architectural modifications to shorten the critical path and to reduce the routing complexity of the FPWD resulting in higher throughput as well as better energy and area efficiency for the modified decoder. The decoder furthermore outperforms a state-of-the-art reference architecture that was implemented for the same code in the same technology in terms of throughput and latency.
Noise Consideration of Radio Receivers Using Silicon Technologies Towards 6G Communication
Mikko Hietanen, Sumit P Singh, Timo Rahkonen and Aarno Pärssinen (University of Oulu, Finland)
Silicon technologies have been the dominant approach to implement radio frequency transceivers up to 5G systems with need for simplified antenna interface in large scale antenna arrays at mm wave region. Recent interests to achieve data rates up to 1 Tbps call for higher carrier frequencies to achieve sufficient bandwidth. Frequencies above 100~GHz will pose serious challenges to silicon based implementations as speed of the transistor in practical designs will not scale up similarly as typically expected in digital signal processing. It’s impacting not only the achievable gain but also on noise of the transistor that directly scales up as a function of frequency impacting the link range. This paper presents specifically behaviour of noise parameter as a function of frequency in transistor level and in simulated low noise amplifiers using state-of-the-art CMOS SOI and SiGe BiCMOS technologies. It will be shown how noise parameter should be considered when evaluating achievable link ranges as a function of the frequency.